

-- @module : alu_tb
-- @author : ben


library ieee;
use ieee.std_logic_1164.all;

entity alu_tb is 
end alu_tb;     
        

architecture synth of alu_tb is
               
component alu port (
	A, B : in bit_vector(31 downto 0);
	add_notSub : in bit;
	Sum : out bit_vector(31 downto 0)
);
end component;   

-- 1 and -1
signal A : bit_vector(31 downto 0) := "11111111111111111111111111111111";
signal B : bit_vector(31 downto 0) := "00000000000000000000000000000001";
signal add_notSub : bit := '1';
signal sum : bit_vector(31 downto 0);    
            
begin  

UUT : alu port map(A, B, add_notSub, sum); 


process 
begin
    
    wait for 50 ns;
    
--10 and 10
A <= "00000000000000000000000000001010";
B <= "00000000000000000000000000001010";

    wait for 50 ns;
    
--sub 20 and 50
add_notSub <= '0';    
A <= "00000000000000000000000000010100";
B <= "00000000000000000000000000110010";

    wait for 50 ns;
    
--sub 20 and 50
add_notSub <= '0';    
A <= "00000000000000000000000000010100";
B <= "00000000000000000000000000110010";

    end process;

end synth;








